Are you developing hardware e.g. for an “Embedded Computer System”? It doesn’t matter for which processor platform – DRAM memory is part of almost all designs. The functionality behind the memory is often unknown. The layout is created according to the design guide, but without background knowledge, it is difficult to judge what effects will come from the design guide. Access to the BIOS on the memory is taken from the CPU manufacturer without the ability to see inside or even make adjustments. This makes troubleshooting quite difficult. The memory interface is becoming more and more of a “black box”! With each new memory generation, the margins become smaller and the demands on the design are increasing.
Join this 3-day in-depth seminar by Teledyne LeCroy and Hermann Ruckerbauer and get the know-how for designing successful products in the future!
Key Topics
- DRAM inside: what’s inside the components?
- Basic commands: how to access the DRAM
- Specification up to Gen5
- Application and compliance test for memory
- Routing and layout: real-world implementation
- (LP)DDR3/4/5: What’s the difference?
- Signal integrity: Simulate your design!
- Power integrity: Improve your PDN design!
- S-Parameter: Read data in the frequency domain!
- ECC: How it works and how to test it?
The lectures, presentations and seminar materials are in English. The seminar is from 9:30 until approx. 16:30.
The seminar days are aimed both at developers who are new to the subject of DDR and at those who already have some experience. There is always something new to discover! During the break, the speakers will of course be available to answer your questions.
You will receive further details about the corresponding event after your registration. We will also send you the invoice.
We look forward to your participation at our seminar!
All participants will receive a certificate of successful participation in the seminar.
DDR Seminar Munich, 20th – 22nd October 2026
Participation fee: EUR 2,400 + VAT (including lunch/coffee breaks)
